1. Field of the Invention
The present invention relates to a short channel transistor fabrication method. In particular, the short channel transistor fabrication method of the invention fabricates transistors having short channels to cope with ultra-fineness of semiconductor devices.
2. Description of the Prior Art
FIG. 1 is a sectional view illustrating a transistor fabrication method for a semiconductor device of the prior art.
As shown in FIG. 1, a gate insulation film 2, a polysilicon layer 3a and a hard mask layer 3b are sequentially layered to a certain height on a semiconductor substrate 1 having a field oxide film (not shown).
The hard mask layer 3b is patterned in the form of a gate electrode, and then the polysilicon layer 3a and the buffer gate insulation film 2 are patterned corresponding to the form of the mask layer 3b so as to form gate regions g.
After spacers 4 are formed at both sides of the gate regions g according to a known method, impurities are doped into the semiconductor substrate 1 outside the spacers so as to form source and drain regions 5.
In the conventional transistor fabrication method for a semiconductor device having the above construction, however, it has been difficult to fabricate the short channel transistor. Also, the above fabrication method disadvantageously requires an additional process in order to overcome Short Channel Effect (SCE) and Drain Induced Barrier Lowering (DIBL) of the transistor.
The present invention has been made to solve the foregoing problems and it is therefore an object of the present invention to provide a short channel transistor fabrication method for a semiconductor device, by which a short channel transistor adequate for an ultrafine device is fabricated via a spacer.
It is another object of the invention to provide a short channel transistor fabrication method for a semiconductor device, in which a Low Doped Drain (LDD) implant region owing to the above spacer can be formed at a distance from a channel region of the transistor so as to reduce SCE and DIBL of the transistor.
It is still another object of the invention to provide a short channel transistor fabrication method for a semiconductor device, which can save manufacturing cost by omitting additional processes for overcoming SCE and DIBL of the transistor from the conventional transistor fabrication method for the semiconductor device.
According to an aspect of the invention for realizing the above objects, a short channel transistor fabrication method for a semiconductor device comprises the following steps of: sequentially forming a first oxide film, a first nitride film, a second oxide film and a second nitride film on a semiconductor substrate; forming a first mask in a proper configuration on the second nitride film; etching the second nitride film and the second oxide film using the first mask; removing the first mask; forming a first spacer film on the resultant structure and etching an entire surface of the first spacer film to form a first spacer at lateral portions of remaining portions of the second oxide and nitride films, wherein the first oxide film is etched using the first spacer as a mask; sequentially forming a gate insulation film and a gate conductor on an exposed portion of the semiconductor substrate and then performing CMP using the remaining second nitride film as a CMP stop layer to form a gate conductor; wet etching the remaining second nitride film, second oxide film, first nitride film and first spacer; performing LDD implantation on an entire surface of the substrate using the gate conductor as a mask to form an LDD region; forming a second spacer film on an entire surface of the substrate including the LDD region and then etching an entire surface of the second spacer film to form a second spacer at a lateral portion of the gate conductor; performing source/drain implantation on an entire surface of the substrate using the gate conductor including the second spacer as a mask to form source/drain regions; removing the remaining first oxide film; and forming a salicide region in the gate conductor and the source/drain regions.
It is preferred that the first spacer film is made of nitride.
It is preferred that the first spacer film is adjusted in width to adjust the size of a channel.
It is preferred that the second spacer film is made of oxide or nitride.
Also, it is preferred that the gate conductor is made of polysilicon or metal.